1. Field of the Invention
The present invention relates generally to integrated circuits and fabrication methods for integrated circuits and, more particularly, to methods of forming overlay alignment structures.
2. Description of Related Art
Since the introduction of semiconductors and fabrication processes for semiconductor devices and integrated circuitry, the density of devices and number of devices on a chip have increased at an exponential rate. With limited space on a semiconductor wafer, the trend has been to construct devices vertically through the use of alternating stacked layers of conductive and non-conductive materials. Layers are patterned through photolithographic processes before additional layers are deposited or grown. A photolithographic process can include depositing a photoresist on top of a layer, positioning a reticle mask (containing a pattern of opaque lines and regions on an otherwise transparent material) over the photoresist, and shining coherent or noncoherent light through the reticle mask onto the photoresist. The light cures the photoresist only where the photoresist is not shadowed by the reticle mask pattern. For positive photoresist any cured photoresist (e.g., the photoresist not shadowed by the reticle mask pattern) is then washed away, exposing regions of the uppermost layer to subsequent processes such as oxidation, metal deposition, and/or impurity doping. Finally, any uncured photoresist is then stripped away, and another photolithography process may begin with another material.
An industry trend toward smaller devices has exacerbated a need to align the subsequent reticle masks more precisely with the previous photolithographic step along the x-y plane as well as rotationally. If, for example, a semiconductor-layer step creates a transistor and then a subsequent metal-layer step is not aligned precisely, a vital connection between the transistor and a conductive path may not be formed.
To facilitate alignment, the first layer on a wafer generally contains a set of alignment marks, which are high precision features that are used to reference the first layer when positioning subsequent layers. Alignment marks are also included in other layers, as the original marks become difficult to align with during further processing. Many fabrication steps include creation of a vernier pattern or other alignment marks on both a reticle mask and the layer to which the reticle mask is to be aligned. Such alignment marks are not necessary for operation of the integrated circuit, but can allow improved alignment of the reticle masks with the substrate.
Vernier patterns are useful alignment structures that comprise a first layer of a plurality of equally spaced rectangles over which a second layer of equally spaced rectangles having a different spacing than the first layer of rectangles is formed. The first layer of rectangles is commonly formed of oxide during for example the field oxidation step. The second layer of rectangles can be formed of photoresist during a subsequent metal deposition step. If, for example, the spacing between the first plurality of rectangles is different than the spacing of the second plurality of rectangles by 0.1 μm, and the top center rectangle aligns to the bottom center rectangle, then perfect alignment is achieved. If however, the top rectangle fourth to the right of center aligns to the bottom rectangle fourth to the right of center, then there is an overlay offset of 0.4 μm in that direction, and the offset can be corrected accordingly.
Common practice is to optically align to the vernier and/or alignment marks through any previously deposited films. With this practice alignment can be difficult to achieve due to optical distortion from reflection and diffraction through the deposited material. The profile of the alignment marks can also change due to expansion or contraction of the deposition film during temperature changes.
FIGS. 1a and 1b illustrate a prior art alignment structure 12 comprising a first overlay mark 14 and a second overlay mark 16 in accordance with a theoretical ideal example and a real world example, respectively. It should be noted that FIGS. 1a and 1b illustrate both plan and cross-sectional views of the prior art alignment structure and that the scales for the plan and cross-sectional views are different. The first overlay mark 14 comprises a metal lined trench 19 and the second overlay mark 16 comprises a first patterned photoresist layer 21. In the stress free ideal condition of FIG. 1a the overlay separations, distance A and distance B, provide the real overlay value. An equal distance A and distance B means that the second overlay mark 16 and its accompanying layer have been correctly positioned. In the real world condition of FIG. 1b compressive and expansive stresses cause the edge profile 27 to shift. Changes in the edge profile 27 cause the first overlay mark 14 to be asymmetric which in turn causes false overlay separation readings of distance A1 and distance B1. In the situation of FIG. 1b the first overlay mark 14 and second overlay mark 16 are properly aligned, but a measurement of the overlay separations indicates that the two overlay marks are not properly aligned due to the edge profile shift. The edge profile shift can create false readings, making it difficult to ascertain actual alignment conditions.
As device dimensions become smaller, the attenuation of errors introduced by optically aligning through the deposition material becomes increasingly important. As such, there is introduced in the art a need to develop a process wherein optical distortion and stress induced measurement error is reduced or eliminated.